In the Very-Large-Scale Integration unit, I have had the chance to use the Cadence design environment and the Virtuoso tool set for full-custom IC design based on the Cadence tool set and the 0.35 um CMOS process from AMS.

Circuit Design using Schematic Entry

  • Create circuit-level schematics using transistors and passives and carry out transient simulations
  • Observing the difference between simulated and calculated values for high-to-low and low-to-high transcient delay, which can be accounted for as the calculation did not consider the internal node capacitance.





    • Layout

  • Construct the layout for a inverter cell(as shown in the fig) and a two-input NOR(NOR2) gate.
  • Use of Cadence Layout XL tool.
  • Minimize NOR2 layout with diffusion sharing techniques. (e.g. Share diffusion regions for PMOS FETs and Share diffusion regions for NMOS FETs)






    • Advanced Simulation and Verification Techniques

  • Build a parameterised cell and simulate it
  • Run parametric analyses and sweeps
  • Quantify effect of parametric variations through corner analyses and Monte Carlo simulations(as shown in the figure)






    • Tasks in Chip Assembly

  • Design of input and output pads, guard rings, and input/output circuits




    • Key Skills developed: