VHDL Peak Detector

The peak detector processes data sequence and returns the peak byte along with the three bytes that precede and follow it. The design was simulated with VHDL program and implemented on Nexys 3 development board with a Spartan 6 device. My main responsibility was to implement the data processor which:

Analysed bytes from data generator and output the peak byte of the sequence;

Maintained the API between different modules in the system;

Took care of various handshaking protocol.

The project familiarised me with real time data processing, concurrent programming and computation efficiency.

VHDL Peak Detector

Key Skills developed:

#VHDL Concurrent Programming #FPGA #Team #Time Management